FPGA COMMUNICATION

UART Communication & DSP Platform

A modular SystemVerilog platform integrating UART communication, FIFO buffering, command parsing, multi-character response control, and DSP visualization.

01 // PROJECT OVERVIEW

System design and implementation

This project implements a complete FPGA communication path between a computer terminal and an Intel MAX 10 FPGA. Incoming UART bytes are buffered, interpreted by a command parser, processed by control logic, and returned through a transmit path. The design was divided into modular RTL blocks so each component could be independently simulated, verified, and integrated.

UART DATA PATH

01PC TERMINAL
02UART RX
038-BYTE FIFO
04COMMAND PARSER
05RESPONSE FSM
06UART TX

PROJECT MEDIA

Hardware, simulation, and demonstrations

Quartus Project Navigator showing the synthesized FPGA design hierarchy and logic utilizationOPEN FULL SIZE ↗
ModelSim waveform showing UART transmit and FIFO signals during simulationOPEN FULL SIZE ↗

TECHNICAL HIGHLIGHTS

01

Implemented UART receive and transmit modules in SystemVerilog.

02

Integrated an 8-byte FIFO for buffered serial communication.

03

Created command parsing and multi-character response control logic.

04

Verified module behavior with ModelSim simulations and waveform analysis.

05

Validated serial communication using physical FPGA hardware and a CP2102 interface.

SOURCE CODE

Review the RTL implementation and supporting files.

OPEN GITHUB →