COMPUTER ARCHITECTURE
8-Bit CPU in SystemVerilog
A modular processor featuring an ALU, four-register file, instruction decoder, program counter, instruction memory, and multi-stage control FSM.
01 // PROJECT OVERVIEW
System design and implementation
This project explores processor architecture through the design of an 8-bit CPU in SystemVerilog. The processor includes a register file, arithmetic logic unit, instruction decoder, program counter, instruction memory, and control state machine. Each subsystem was designed and tested separately before being integrated into the complete processor.
PROCESSOR DATA PATH
01PROGRAM COUNTER
02INSTRUCTION ROM
03DECODER
04REGISTER FILE
05ALU
06WRITEBACK
PROJECT MEDIA
Hardware, simulation, and demonstrations
TECHNICAL HIGHLIGHTS
01
Designed an 8-bit arithmetic logic unit supporting core processor operations.
02
Implemented a four-register storage architecture.
03
Created instruction decode and processor control logic.
04
Developed a multi-stage FSM for instruction execution.
05
Simulated processor behavior and validated the integrated design on FPGA hardware.
SOURCE CODE
Review the RTL implementation and supporting files.